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44 - pin plastic 7mm x 7mm chip-scale package (qfn) features arinc specification 429 compliant 3.3v or 5.0v logic supply operation directly to arinc 429 bus programmable label recognition for 256 labels 32 x 32 receive fifo and 32 x 32 transmit fifo high-speed, four-wire serial peripheral interface label bit-order control 32nd transmit bit can be data or parity self test mode low power industrial & extended temperature ranges on-chip analog line driver and receiver connect independent data rates for transmit and receive general description the hi-3585 from holt integrated circuits is a silicon gate cmos device for interfacing a serial peripheral interface (spi) enabled microcontroller to the arinc 429 serial bus. the device provides one receiver with user-programmable label recognition for any combination of 256 possible labels, 32 x 32 receive fifo and analog line receiver. the independent transmitter has a 32 x 32 transmit fifo and built-in line driver. the status of the transmit and receive fifos can be monitored using the programmable external interrupt pin, or by polling the hi-3585 status register. other features include a programmable option of data or parity in the 32nd bit, and the ability to switch the bit-signifiance of arinc 429 labels. pins are available with different input resistance and output resistance values which provides flexibility when using external lightning protection circuitry. the serial peripheral interface minimizes the number of host interface signals resulting in a small footprint device that can be interfaced to a wide range of industry-standard microcontrollers supporting spi. alternatively, the spi signals may be controlled using just four general purpose i/o port pins from a microcontroller or custom fpga. the spi and all control signals are cmos and ttl compatible and support 3.3v or 5v operation. the hi-3585 applies the arinc 429 protocol to the receiver and transmitter. arinc 429 databus timing comes from a 1 mhz clock input, or an internal counter can derive it from higher clock frequencies having certain fixed values, possibly the external host processor clock. the hi-3586 is functionally identical to the hi-3585 except it includes digital transmitter output pins 429d1 and 429d0 instead of a built-in line driver. this allows the designer to take advantage of holt?s single supply rail line drivers, such as the 5v hi-8592 or 3.3v hi-8596. pin configurations (top view) arinc 429 terminal ic with spi interface july 2013 hi-3585, hi-3586 (ds3585 rev. j) 07/13 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - n/c 38 - v+ 37 - n/c 36 - aout27 35 - aout37 34 - n/c n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c - 10 n/c - 11 cs 33 - bout27 32 - bout37 31 - n/c 30 - v- 29 - n/c 28 - tflag 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c - 12 n/c - 13 n/c - 14 sck - 15 n/c - 16 gnd - 17 n/c - 18 aclk - 19 so - 20 n/c - 21 n/c - 22 HI-3585PCI hi-3585pct holt integrated circuits www.holtic.com
429d0 (hi-3586 only) 429d1(hi-3586 only) signal function description note rinb input arinc receiver negative input. direct connection to arinc 429 bus rinb-40 input alternate arinc receiver negative input. requires external 40k ohm resistor mr input master reset. a positive pulse clears receive and transmit data fifos and flags 10k ohm pull-down* si input spi interface serial data input 10k ohm pull-down* input chip select. data is shifted into si and out of so when is low. 10k ohm pull-up* sck input spi clock. data is shifted into or out of the spi interface using sck 10k ohm pull-down* gnd power chip 0v supply aclk input master timing source for the arinc 429 receiver and transmitter 10k ohm pull-down* so output spi interface serial data output rflag output goes high when arinc 429 receive fifo is empty (cr15=0), or full (cr15=1) tflag output goes high when arinc 429 transmit fifo is empty (cr14=0), or full (cr14=1) v- power minus 5v power supply to arinc 429 line driver (hi-3585 only) bout37 output arinc line driver negative output. direct connection to arinc 429 bus (hi-3585 only) bout27 output alternate arinc line driver negative output. requires external 10 ohm resistor (hi-3585 only) aout27 output alternate arinc line driver positive output. requires external 10 ohm resistor (hi-3585 only) aout37 output arinc line driver positive output. direct connection to arinc 429 bus (hi-3585 only) v+ power positive 5v power supply to arinc 429 line driver (hi-3585 only) vdd power 3.3v or 5.0v logic power rina-40 input alternate arinc receiver positive input. requires external 40k ohm resistor rina input arinc receiver positive input. direct connection to arinc 429 bus 429d1 output digital positive output to external line driver (hi-3586 only) 429d0 output digital negative output to external line driver (hi-3586 only) * internal pull-up or pull-down cs cs pin descriptions vdd aout27 bout27 spi interface aout37 bout37 control register status register arinc 429 transmit data fifo arinc 429 transmit formatter arinc 429 line driver (hi-3585 only) arinc 429 received data fifo label filter arinc 429 valid word checker arinc 429 line receiver label filter bit map memory rina-40 rina rinb rinb-40 sck cs si so v- rflag aclk gnd tflag v+ 40 kohm 40 kohm 27 ohm 10 ohm 10 ohm 27 ohm arinc clock divider block diagram hi-3585, hi-3586 holt integrated circuits 2
example: one spi instruction op code 07hex data field 02hex msb lsb msb lsb cs sck si instructions instruction op codes are used to read, write and configure the hi- 3585. when goes low, the next 8 clocks at the sck pin shift an instruction op code into the decoder, starting with the first positive edge. the op code is fed into the si pin most significant bit first. for write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising sck edge. data word length varies depending on word type written: 16-bit writes to control register, 32-bit arinc word writes to transmit fifo or 256-bit writes to the label-matching enable/disable table. cs for read instructions, the most significant bit of the requested data word appears at the so pin after the last op code bit is clocked into the decoder, at the next falling sck edge. as with write instructions, data field bit-length varies with read instruction type. table 1 lists all instructions. instructions that perform a reset or set, or enable transmission are executed after the last si bit is received while is still low. cs op code hex 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 10 11 12 data field none none none none 8 bits 8 bits 256 bits 8 bits 32 bits none 8 bits 16 bits 8 bits 256 bits n x 32 bits none 16 bits none none description no instruction implemented after the 8th op code bit is received, perform master reset (mr) , reset all label selections , set all the label selections reset the label at the address specified in the data field set starting with label ff hex, consecutively set or reset each label in descending order for example, a data field pattern starting with 1011 will set labels ff, fd, and fc hex and reset label fe hex programs a division of the aclk input. if the divided aclk frequency is 1 mhz and control register bit cr1 is set, the arinc receiver and transmitter operate from the divided aclk clock. allowable values for division rate are x1, x2, x4, x8, or xa hex. any other programmed value results in no clock. note: aclk input frequency and division ratio must yield 1 mhz clock. read the next word in the receive fifo. if the fifo is empty, it will read zeros no instruction implemented read the status register read the control register read the aclk divide value programmed previously using op code 07 hex read the label look-up memory table consecutively starting with address ff hex. write up to 32 words into the next empty positions of the transmit fifo no instruction implemented write the control register reset the transmit fifo. , the transmit fifo will be empty transmission enabled by this instruction only if control register bit 13 is zero after the 8th op code bit is received after the 8th op code bit is received the label at the address specified in the data field after the 8th op code bit is received table 1. defined instruction op codes hi-3585, hi-3586 holt integrated circuits 3
control word register the hi-3585 contains a 16-bit control register which is used to configure the device. control register bits cr15 - cr0 are loaded from a 16-bit data value appended to spi instruction 10 hex. the control register contents may be read using spi instruction 0b hex. each bit of the control register has the following function: status register the hi-3585 contains an 8-bit status register which can be interrogated to determine the status of the arinc receiver, data fifos and transmitter. the contents of the status register are output using spi instruction 0a hex. unused bits are output as zeros. the following table defines the status register bits. sr bit function state description sr0 receive fifo 0 1 receiver fifo is empty receiver fifo contains valid data (lsb) empty sets to one when all data has been read. rflag pin reflects the state of this bit when cr15=0 sr1 receive fifo 0 receiver fifo holds less than 16 half full words 1 receiver fifo holds at least 16 words sr2 receive fifo 0 receiver fifo not full. rflag pin full reflects the state of this bit when cr15=1 1 receiver fifo full. to avoid data loss, the fifo must be read within one arinc word period sr3 transmit fifo 0 transmit fifo not empty. empty sets to one when all data has been sent. tflag pin reflects the state of this bit when cr14=0 1 transmit fifo is empty. sr4 transmit fifo 0 transmit fifo contains less than 16 half full words 1 transmit fifo contains at least 16 words sr5 transmit fifo 0 transmit fifo not full. tflag pin full reflects the state of this bit when cr14=1 1 transmit fifo full. sr6 not used 0 always ?0? sr7 not used 0 always ?0? (msb) cr bit function state description cr0 receiver 0 data rate = clk/10 1 data rate = clk/80 (arinc 429 high-speed) (lsb) data rate select (arinc 429 low-speed) cr1 arinc clock 0 arinc clk = aclk input frequency source select 1 arinc clk = aclk divided by the value programmed with spi instruction 07 hex cr2 enable label 0 label recognition disabled recognition 1 label recognition enabled cr3 transmitter 0 transmitter 32nd bit is data parity bit enable 1 transmitter 32nd bit is parity cr4 receiver 0 receiver parity check disabled parity check enable 1 receiver odd parity check enabled cr5 self test 0 the transmitter?s digital outputs are internally connected to the receiver logic inputs 1 normal operation cr6 receiver 0 receiver decoder disabled decoder 1 arinc bits 10 and 9 must match cr7 and cr8 cr7 - - if receiver decoder is enabled, the arinc bit 10 must match this bit cr8 - - if receiver decoder is enabled, the arinc bit 9 must match this bit cr9 transmitter 0 transmitter 32nd bit is odd parity parity select 1 transmitter 32nd bit is even parity cr10 transmitter 0 data rate = clk/10, o/p slope = 1.5us data rate 1 data rate = clk/80, o/p slope = 10us cr11 arinc label 0 label bit order reversed (see table 2) bit order 1 label bit order same as transmitted / received (see table 2) cr12 disable 0 line driver enabled line driver 1 line driver disabled (force outputs to null state) cr13 transmission 0 start transmission by spi enable mode instruction12 hex 1 transmit whenever data is available in the transmit fifo cr14 tflag 0 tflag goes high when transmit fifo is empty definition 1 tflag goes high when transmit fifo is full cr15 rflag 0 rflag goes high when receive fifo is empty (msb) definition 1 rflag goes high when receive fifo is full functional description hi-3585, hi-3586 holt integrated circuits 4
1. an accurate 1mhz clock source is required to validate the receive signal timing. less than 1% error is recommended. 2. the receiver uses three separate 10-bit sampling shift reg- isters for ones detection, zeros detection and null detection. when the input signal is within the differential voltage range for any shift register?s state (one zero or null) sampling clocks a high bit into that register. when the receive signal is outside the differential voltage range defined for any shift reg- ister, a low bit is clocked. only one shift register can clock a high bit for any given sample. all three registers clock low bits if the differential input voltage is between defined state voltage bands. valid data bits require at least three consecutive one or zero samples (three high bits) in the upper half of the ones or zeros sampling shift register, and at least three consecutive null samples (three high bits) in the lower half of the null sam- pling shift register within the data bit interval. a word gap null requires at least three consecutive null sam- ples (three high bits) in the upper half of the null sampling shift register and at least three consecutive null samples (three high bits) in the lower half of the null sampling shift reg- ister. this guarantees the minimum pulse width. receiver logic operation bit timing bit rate pulse rise time pulse fall time pulse width figure 2 is a block diagram showing receiver logic. the arinc 429 specification defines the following timing toler- ances for received data: 100k bps 1% 12k -14.5k bps 1.5 0.5 sec 10 5 sec 1.5 0.5 sec 10 5 sec 5 sec 5% 34.5 to 41.7 sec the hi-3585 accepts signals within these tolerances and rejects signals outside these tolerances. receiver logic achieves this as described below: high speed low speed 3. to validate the receive data bit rate, each bit must follow its preceding bit by not less than 8 samples and not more than 12 samples. with exactly 1mhz input clock frequency, the acceptable data bit rates are: 83k bps 10.4k bps 125k bps 15.6k bps 4. following the last data bit of a valid reception, the word gap timer samples the null shift register every 10 input clocks (every 80 clocks for low speed). if a null is present, the word gap counter is incremented. a word gap count of 3 enables the next reception. high speed low speed data bit rate min data bit rate max functional description (cont.) arinc 429 receiver arinc bus interface figure 1 shows the input circuit for the on-chip arinc 429 line receiver. the arinc 429 specification requires the following detection levels: one +6.5 volts to +13 volts null +2.5 volts to -2.5 volts zero -6.5 volts to -13 volts state differential voltage differential amplifiers comparators figure 1. arinc receiver input rina-40 rina rinb rinb-40 vdd gnd vdd gnd one null zero the hi-3585 guarantees recognition of these levels with a common mode voltage with respect to gnd less than 30v for the worst case condition (3.15v supply and 13v signal level). design tolerances guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. if the arinc signal (including nulls) is outside the differential voltage ranges, the hi- 3585 receiver rejects the data. hi-3585, hi-3586 parity sdi label label (lsb) label (msb) label label label label label sdi parity sdi label label (msb) label (lsb) label label label label label sdi arinc 429 data format control register bit cr11 controls how individual bits in the received or transmitted arinc word are mapped to the hi-3585 spi data word bits during data read or write operations. the following table describes this mapping: table 2. spi / arinc bit-mapping spi 1 2-22 23242526272829303132 order . arinc bit 32 31 - 11 10 912345678 cr11=0 data arinc bit 32 31 - 11 10 987654321 cr11=1 data holt integrated circuits 5
fifo load control control bits cr2, cr6-8 / spi interface 32 bit shift register controlbits cr0, cr1 clock option clock aclk bit counter and end of sequence parity check 32nd bit data bit clock word gap word gap timer bit clock end start sequence control error clock error detection shift register shift register null zeros shift register ones eos figure 2. receiver block diagram label / decode compare 256-bit label look-up table 32x32 fifo rflag sck cs si so functional description (cont.) hi-3585, hi-3586 holt integrated circuits 6
0 x 0 x load fifo 1 no 0 x ignore data 1 yes 0 x load fifo 0 x 1 no ignore data 0 x 1 yes load fifo 1 yes 1 no ignore data 1 no 1 yes ignore data 1 no 1 no ignore data 1 yes 1 yes load fifo cr2 arinc word cr6 arinc word fifo matches bits 10, 9 enabled match cr7, 8 label retrieving data once 32 valid bits are recognized, the receiver logic generates an end of sequence (eos). depending on the state of control register bits cr2, cr6, cr7 and cr8, the received 32-bit arinc word is then checked for correct decoding and label match before it is loaded into the 32 x 32 receive fifo. arinc words that do not match required 9th and 10th arinc bit and do not have a label match are ignored and are not loaded into the receive fifo. the adjacent table describes this operation. once a valid arinc word is loaded into the fifo, the eos signal clocks the data ready flip-flop to a "1" and status register bit 0 (sr0) to a ?0?. the sr0 bit remains low until the receive fifo is empty. each received arinc word is retrieved via the spi interface using spi instruction 08 hex to read a single word. up to 32 arinc words may be held in the receive fifo. status register bit 2 (sr2) goes high when the receive fifo is full. failure to unload the receive fifo when full causes additional received valid arinc words to overwrite receive fifo location 32. a fifo half-full flag (sr1) is high when the receive fifo contains 16 or more arinc words. sr1 may be interrogated by the system?s external microprocessor, allowing a 16 word data retrieval routine to be performed. functional description (cont.) table 3. fifo loading control hi-3585, hi-3586 holt integrated circuits 7 receiver parity the receiver parity check enable bit (control register bit 4, cr4) controls how the 32nd bit of the received arinc word is interpreted by the hi-3585 receiver. , the 32nd bit is treated as data and transferred as received from the arinc bus to the receive fifo. , the 32nd bit is treated as a parity error bit. the receiver expects the 32nd bit of the received word to indicate odd parity. if this is the case, the parity bit is reset to indicate correct parity was received and resulting word is written to the receive fifo. if the received word is even parity, the receiver sets the 32nd bit to a ?1?, indicating a parity error. the resulting word is then written to the receive fifo. therefore, when cr4 is set to ?1?, the 32nd bit retrieved from the receiver fifo will always be ?0? when valid (odd parity) arinc 429 words are received. when cr4 is set to a ?0? when cr4 is set to a ?1? odd parity received even parity received 0 data data 1 parity bit 0 = odd parity 1= odd parity error (even parity) cr4 arinc bus fifo 32nd bit 32nd bit error bit: label recognition the user loads the 256-bit label look-up table to specify which 8-bit incoming arinc labels are captured by the receiver, and which are discarded. setting a ?1? in the look-up table enables processing of received arinc words containing the corresponding label. a ?0? in the look-up table causes discard of received arinc words containing the label. the 256-bit look-up table is loaded using spi op codes 02 hex, 03 hex or 06 hex, as described in table 1. after the look-up table is initialized, set control register bit cr2 to enable label recognition. if label recognition is enabled, the receiver compares the label in each new arinc word against the stored look-up table. if a label match is found, the received word is processed. if no match occurs, the new arinc word is discarded and no indicators of received arinc data are presented. the contents of the label look-up table may be read via the spi interface using instruction 0d hex as described in table 1. reading the label look-up table
the hi-3586 is functionally identical to the hi-3585 except it does not include an on-chip arinc 429 line driver. instead, digital output pins 429d1 and 429d0 may be used to drive an external arinc 429 line driver. this configuration is useful if the desiger wishes to take advantage of holt?s single supply rail line drivers, such as the 5v hi-8592 or 3.3v hi-8596. hi-3586 option arinc 429 bus hi-3586 hi-3586 / hi-8596 3.3v-only design example gnd 3.3v 32.5 ohm 32.5 ohm 429d1 429d0 hi-8596 tx1in tx0in txaout txbout functional description (cont.) transmitter fifo operation the transmit fifo is loaded with arinc 429 words awaiting transmission. spi op code 0e hex writes up to 32 arinc words into the fifo, starting at the next available fifo location. if status register bit sr3 equals ?1? (fifo empty), then up to 32 words (32 bits each) may be loaded. if status register bit sr3 equals ?0? then only the available positions may be loaded. if all 32 positions are full, status register bit sr5 is asserted. further attempts to load the transmit fifo are ignored until at least one arinc word is transmitted. the transmit fifo half-full flag (status register bit sr4) equals ?0? when the transmit fifo contains less than 16 words. when sr4 equals ?0?, the system microprocessor can safely initiate a 16-word arinc block-write sequence. in normal operation (control register bit cr3 = ?1?), the 32nd bit transmitted is a word parity bit. odd or even parity is selected by programming control register bit cr9 to a ?0? or ?1? respectively. if control register bit cr3 equals ?0?, all 32 bits loaded into the transmit fifo are treated as data and are transmitted. spi op code 11 hex asynchronously clears all data in the transmit fifo. the transmit fifo should be cleared after a self-test before starting normal operation to avoid inadvertent transmission of test data. cr3, cr9 figure 3. transmitter block diagram data clock cr10, cr1 aclk parity generator data and null timer sequencer line driver bit and word gap counter start sequence word counter and fifo control increment word count data clock divider fifo loading sequencer aout bout 32 x 32 fifo 32 bit parallel load shift register bit clock word clock address load sr3 cr12 sr4 sr5 spi interface sck cs si so spi commands spi commands hi-3585, hi-3586 holt integrated circuits 8
functional description (cont.) data transmission transmitter parity self test system operation line driver operation line driver output pins line receiver input pins power supply sequencing master reset (mr) if control register bit cr13 equals ?1?, arinc 429 data is transmitted immediately following the rising edge of the spi instruction that loaded data into the transmit fifo. loading control register bit cr13 to ?0? allows the software to control transmission timing; each time an spi op code 12 hex is executed, all loaded transmit fifo words are transmitted. if new words are loaded into the transmit fifo before transmission stops, the new words will also be output. once the transmit fifo is empty and transmission of the last word is complete, the fifo can be loaded with new data which is held until the next spi 12 hex instruction is executed. once transmission is enabled, the fifo positions are incremented with the top register loading into the data transmission shift register. within 2.5 data clocks the first data bit appears at aout and bout. the 31 or 32 bits in the data transmission shift register are presented sequentially to the outputs in the arinc 429 format with the following timing: the word counter detects when all loaded positions have been transmitted and sets the transmitter ready flag, sr3, high. the parity generator counts the ones in the 31-bit word. if control register bit cr9 is set to a ?0?, the 32nd bit transmitted will make parity odd. if the control bit is a ?1?, the parity is even. setting cr3 to ?0? bypasses the parity generator, and allows 32 bits of data to be transmitted. if control register bits cr5 and cr12 equal ?0?, the transmitter serial output data is internally looped-back into the receiver. data passes unmodified from transmitter to receiver. setting control register bit cr12 to ?1? forces aout and bout to the null state regardless of cr5 state. the receiver is independent of the transmitter. therefore, control of data exchanges is strictly at the option of the user. the only restrictions are: 1. the received data will be overwritten if the receive fifo is full and at least one location is not retrieved before the next complete arinc word is received. 2. the transmit fifo can store 32 words maximum and ignores attempts to load additional data when full. the line driver in the hi-3585 directly drives the arinc 429 bus. the two arinc outputs (aout37 and bout37) provide a differential voltage to produce a +10v one, a -10v zero, and a 0 volt null. control register bit cr10 controls both the transmitter data rate and the slope of the differential output signal. no additional hardware is required to control the slope. transmit timing is derived from a 1 mhz reference clock. control register bit cr1 determines the reference clock source. if cr1 equals ?0,? a 50% duty cycle 1 mhz clock should be applied to the aclk input pin. if cr1 equals ?1,? the aclk input is divided to generate the 1 mhz arinc clock. spi op code 07 hex provides the hi-3585 with the correct division ratio to generate a 1 mhz reference from aclk. loading control register bit cr10 to ?0? causes a 100 kbit/s data rate and a slope of 1.5 s on the arinc outputs. loading cr10 to ?1? causes a 12.5 kbit/s data rate and a slope of 10 s. timing is set by an on-chip resistor and capacitor and tested to be within arinc 429 requirements. the hi-3585 aout37 and bout37 pins have 37.5 ohms in series with each line driver output, and may be directly connected to an arinc 429 bus. the alternate aout27 and bout27 pins have 27 ohms of internal series resistance and require external 10 ohm resistors at each pin. aout27 and bout27 are for applications where external series resistance is applied, typically for lightning protection devices. please refer to the holt an-300 application note for additional information and recommendations on lightning protection of holt line drivers and line receivers. power supply sequencing should be controlled to prevent large currents during supply turn-on and turn-off. the recommended sequence is v+ followed by v , always ensuring that v+ is the most positive supply. the v- supply is not critical and can be applied at any time. application of a master reset causes immediate termination of data transmission and data reception. the transmit and receive fifos are cleared. status register fifo flags and fifo status output signals rflag and tflag are also cleared. the control register is not affected by a master reset. cs arinc data bit time 10 clocks 80 clocks data bit time 5 clocks 40 clocks null bit time 5 clocks 40 clocks word gap time 40 clocks 320 clocks high speed low speed the hi-3585 has two sets of line receiver input pins, rina/b and rina/b-40. only one pair may be used to connect to the arinc 429 bus. the unused pair must be left floating. the rina/b pins may be connected directly to the arinc 429 bus. the rina/b-40 pins require external 40k ohm resistors in series with each arinc input. these do not affect the arinc receiver thresholds. by keeping excessive voltage outside the device, this option is helpful in applications where lightning protection is re- quired. when using the rina/b-40 pins, each side of the arinc bus must be connected through a 40k ohm series resistor in order for the chip to detect the correct arinc levels. the typical 10 volt dif- ferential signal is translated and input to a window comparator and latch. the comparator levels are set so that with the external 40k ohm resistors, they are just below the standard 6.5 volt mini- mum arinc data threshold and just above the standard 2.5 volt maximum arinc null threshold. dd hi-3585, hi-3586 holt integrated circuits 9
msb lsb msb lsb high z high z cs so si 01234567 sck (spi mode 0) figure 4. generalized single-byte transfer using spi protocol mode 0 serial peripheral interface (spi) basics the hi-3585 uses an spi synchronous serial interface for host access to internal registers and data fifos. host serial communication is enabled through the chip select ( ) pin, and is accessed via a three-wire interface consisting of serial data input (si) from the host, serial data output (so) to the host and serial clock (sck). all read / write cycles are completely self- timed. the spi (serial peripheral interface) protocol specifies master and slave operation; the hi-3585 operates as an spi slave. the spi protocol defines two parameters, cpol (clock polarity) and cpha (clock phase). the possible cpol-cpha combinations define four possible "spi modes". without describing details of the spi modes, the hi-3585 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of sck, and output data for each device changes on the falling edge (cpha = 0, cpol = 0). be sure to set the host spi logic for mode 0. as seen in figure 4, spi mode 0 holds sck in the low state when idle. the spi protocol transfers serial data as 8-bit bytes. once chip select is asserted, the next 8 rising edges on sck latch input data into the master and slave devices, starting with each byte?s most-significant bit. multiple bytes may be transferred when the host holds low after the first byte transferred, and continues to clock sck in multiples of 8 clocks. a rising edge on chip select terminates the serial transfer and reinitializes the hi-3585 spi for the next transfer. if goes high before a full byte is clocked by sck, the incomplete byte clocked into the device si pin is discarded. in the general case, both master and slave simultaneously send and receive serial data (full duplex), per figure 4 below. however the hi-3585 operates half duplex, maintaining high impedance on the so output, except when actually transmitting serial data. when the hi-3110 is sending data on so during read operations, activity on its si input is ignored. figures 5 and 6 show actual behavior for the hi-3585 so output. cs cs cs cs cs serial peripheral interface holt integrated circuits 10 hi-3585, hi-3586
figure 6. 2-byte write example cs so si sck spi mode 0 msb lsb 0 12 3 4 5 67 high z 0 12 3 4 5 670 12 3 4 5 67 msb lsb msb lsb data byte 0 data byte 1 op-code byte host may continue to assert here to write sequential byte(s) when allowed by the spi instruction. each byte needs 8 sck clocks. cs figure 5. single-byte read from a register cs so si sck msb lsb 0 12 3 4 5 67 high z high z 0 12 3 4 5 67 msb lsb msb lsb data byte op-code byte host may continue to assert here to read sequential word(s) when allowed by the instruction. each word needs 8 sck clocks. cs hi-3585 spi commands for the hi-3585, each spi read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of . since hi-3585 command byte reception is half- duplex, the host discards the dummy byte it receives while serially transmitting the command byte. figures 5 and 6 show read and write timing as it appears for a single-byte and dual-byte register operation. the command byte is immediately followed by a data byte comprising the 8-bit data word read or written. for a single register read or write, is negated after the data byte is transferred. multiple byte read or write cycles may be performed by transferring more than one byte before is negated. table 1 defines the required number of bytes for each instruction. note: spi instruction op-codes not shown in tables 1 are ?reserved? and must not be used. further, these op-codes will not provide meaningful data in response to read commands. ; must be negated after the command, then reasserted for the following read or write command. cs cs cs cs two instruction bytes cannot be ?chained? host serial peripheral interface (cont.) holt integrated circuits 11 hi-3585, hi-3586
receiver operation rflag arinc data cs si bit 31 bit 32 rflg t arinc bit 32 spif t so spi instruction 08h arinc bit 31 arinc bit 30 rxr t data rate - example pattern txaout arinc bit txbout null data data data null null word gap bit 1 next word bit 32 bit 31 bit 30 serial output timing diagram cs sck so chz t hi impedance t dv lsb cph t msb hi impedance serial input timing diagram cs sck si chh t ceh t msb ces t ds tt dh lsb cph t sckr t sckf t timing diagrams hi-3585, hi-3586 * above diagram does not apply for op code instruction 09hex arinc bit 1 holt integrated circuits 12 ces t cyc t cyc t
supply voltages v ......................................... -0.3v to +7.0v v+ ......................................................... +7.0v v- ......................................................... -7.0v voltage at pins rina, rinb ............................... -120v to +120v voltage at any other pin ............................... -0.3v to v +0.3v solder temperature (leads) .................... 280 for 10 seconds (package) .......................................... 220 dd dd c c power dissipation at 25c plastic quad flat pack ..................1.5 w, derate 10mw/ c dc current drain per pin .............................................. 10ma operating temperature range (industrial): ..... -40c to +85c (hi-temp): ..... -55c to +125c storage temperature range ........................ -65c to +150c note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings transmitting data arinc bit arinc bit arinc bit cs tflag (cr14=0) aout bout diff v (aout - bout) +5v +5v +5v +10v +10v -10v -5v -5v -5v si datt t data bit 1 data bit 2 data bit 32 one level zero level null level 90% 90% 10% 10% t fx t rx t fx t rx sdat t tflg t spi instruction 0eh, (or 12h) timing diagrams (cont.) hi-3585, hi-3586 holt integrated circuits 13
arinc outputs - pins aout37, bout37, (or aout27, bout27 with external 10 ohms) logic outputs operating voltage range operating supply current output voltage: logic "1" output voltage v i = -100 a v logic "0" output voltage v i = 1.0ma v output current: output sink i v = 0.4v 1.6 ma output source i v = v - 0.4v -1.0 ma output capacitance: c 15 pf vdd 3.15 5.25 v v+ 4.75 5.5 v v- -4.75 -5.5 v vdd i 2.5 7 ma arinc output voltage (ref. to gnd) one or zero v no load and magnitude at pin, 4.50 5.00 5.50 v null v -0.25 0.25 v arinc output voltage (differential) one or zero v no load and magnitude at pin, 9.0 10.0 11.0 v null v -0.5 0.5 v arinc output current i momentary current 80 ma v+ i 4 14 ma v- i 4 12 ma dout nout ddif ndif out dd2 ee1 oh oh ol ol ol out oh out dd o dd1 90%vdd 10% vdd limits parameter conditions unit symbol differential input voltage: one v common mode voltages 6.5 10.0 13.0 v (rina to rinb) zero v less than 30v with -13.0 -10.0 -6.5 v null v respect to gnd -2.5 0 2.5 v input resistance: differential r - 140 - k to gnd r - 140 - k to v r - 100 - k input current: input sink i 200 a input source i -450 a input capacitance: differential c 20 pf (guaranteed but not tested) to gnd c 20 pf to v c 20 pf input voltage: input voltage hi v v input voltage lo v v input current: input sink i 1.5 a input source i -1.5 a min typ max arinc inputs - pins rina, rinb, rina-40 (with external 40kohms), rinb-40 (with external 40kohms) logic inputs ih il nul i g dd h ih il i g dd h ih il ih il (rina to rinb) pull-down current (mr, si, sck, aclk pins) i 250 600 a pull-up current (cs pin) i -600 -300 a 80% vdd 20% vdd pd pu v = 3.3v or 5.0v , gnd = 0v, ta = operating temperature range (unless otherwise specified). dd v+ = +5v, v- = -5v, dc electrical characteristics hi-3585, hi-3586 holt integrated circuits 14
ac electrical characteristics vdd = 3.3v or 5.0v, v+=+5v, v-=-5v, gnd = 0v, ta = operating temperature range and fclk=1mhz 0.1% with 50/50 duty cycle + limits parameter symbol units min typ max spi interface timing - 5.0v receiver timing sck clock period active after last sck rising edge t 10 ns setup time to first sck rising edge t 10 ns hold time after last sck falling edge t 40 ns inactive between spi instructions t delay - last bit of received arinc word to rflag(full or empty) - hi speed t 16 s received data available to spi interface. rflag to active spi receiver read or clear fifo instruction to rflag t spi transmit data write or fifo clear instruction to tflag (empty or full) t spi instruction to arinc 429 data output - hi speed t delay tflag high after enable transmit - hi speed line driver transition differential times: high to low t 1.0 1.5 2.0 t 250 ns 20 ns spi si data set-up time to sck rising edge t 25 ns spi si data hold time after sck rising edge t 15 ns sck rise time t 10 ns sck fall ime t 10 ns so valid after sck falling edge t 125 ns so high-impedance after sck falling edge t 100 ns master reset pulse width t 150 ns sck clock period t 390 ns active after last sck rising edge t 10 ns setup time to first sck rising edge t 10 ns hold time after last sck falling edge t 40 ns inactive between spi instructions t 35 ns spi si data set-up time to sck rising edge t 30 ns spi si data hold time after sck rising edge t 30 ns sck rise time t 10 ns sck fall ime t 10 ns so valid after sck falling edge t 195 ns so high-impedance after sck falling edge t 100 ns master reset pulse width t 150 ns delay - last bit of received arinc word to rflag(full or empty) - lo speed t 126 s t0 ns 155 ns 120 ns 17 s spi instruction to arinc 429 data output - lo speed t 118 s t14s delay tflag high after enable transmit - lo speed t 114 s (high speed, control register cr10 = logic 0) s low to high t 1.0 1.5 2.0 s (low speed, control register cr10 = logic 1) high to low t 5.0 10 15 s low to high t 5.0 10 15 s cyc cph ds dh sckr sckf dv chz cyc chh ces ceh cph ds dh sckr sckf dv chz rflg rxr sdat datt datt rx fx rx cs cs cs cs cs chh ces ceh rflg spif tflg sdat fx mr mr spi interface timing - 3.3v transmitter timing cs cs cs cs hi-3585, hi-3586 holt integrated circuits 15
holt integrated circuits 16 hi-3585, hi-3586 44 - pin plastic 7mm x 7mm chip-scale package (qfn) additional hi-3585 & hi-3586 pin configurations (top view) 44 - pin plastic quad flat pack (pqfp) 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - 429d1 38 - 429d0 37 - vdd 36 - n/c 35 - n/c 34 - n/c n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c - 10 n/c - 11 cs 33 - n/c 32 - n/c 31 - n/c 30 - gnd 29 - n/c 28 - tflag 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c - 12 n/c - 13 n/c - 14 sck - 15 n/c - 16 gnd - 17 n/c - 18 aclk - 19 so - 20 n/c - 21 n/c - 22 hi-3586pci hi-3586pct 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - 429d1 38 - 429d0 37 - vdd 36 - n/c 35 - n/c 34 - n/c 33 - n/c 32 - n/c 31 - n/c 30 - gnd 29 - n/c 28 - tflag 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c-12 n/c-13 n/c-14 sck-15 n/c-16 gnd-17 n/c-18 aclk - 19 so-20 n/c-21 n/c-22 n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c-10 n/c-11 cs hi-3586pqi hi-3586pqt hi-3586pqm 44 - pin plastic quad flat pack (pqfp) 44 - n/c 43 - rina 42 - rina-40 41 - n/c 40 - vdd 39 - n/c 38 - v+ 37 - n/c 36 - aout27 35 - aout37 34 - n/c 33 - bout27 32 - bout37 31 - n/c 30-v- 29 - n/c 28 - tflag 27 - n/c 26 - n/c 25 - rflag 24 - n/c 23 - n/c n/c-12 n/c-13 n/c-14 sck-15 n/c-16 gnd-17 n/c-18 aclk - 19 so-20 n/c-21 n/c-22 n/c - 1 rinb-40 - 2 rinb - 3 n/c - 4 n/c - 5 n/c - 6 mr - 7 si - 8 -9 n/c-10 n/c-11 cs hi-3585pqi hi-3585pqt hi-3585pqm
ordering information hi - 358x xx x x package description 44 pin plastic chip-scale, qfn (44pcs) not avaiable in ?m? flow part number pc 44 pin plastic quad flat pack, pqfp (44ptqs) pq lead finish part number 100% matte tin (pb-free, rohs compliant) f tin / lead (sn / pb) solder blank temperature range -40c to +85c no -55c to +125c no t part number t i flow i holt integrated circuits 17 hi-3585, hi-3586 package description on-chip arinc 429 line driver part number 3585 external arinc 429 line driver 3586 -55c to +125c yes m m
hi-3585, hi-3586 revision history p/n rev date description of change ds3585 new 05/08/08 initial release a 10/10/08 revised ac electrical characteristics table and description of ?t? process. b 05/22/09 clarified relationship between spi bit order and the arinc 429 bit order. c 02/03/10 clarified op code 09 hex description. d 04/20/10 removed op code 09 hex. e 05/19/10 corrected arinc receiver nomenclature. f 09/03/10 added hi-3586 digital-only product option g 11/02/10 enhanced description of hi-3586 digital-only product option, added basics of spi communications and added m flow for qfp package. h 06/04/12 clarified the description of receiver parity. updated pqfp package drawing. corrected typo in clock source tolerance on p. 5 from 0.1% to 1%. i 07/02/12 update spi interface timing at 5.0v and 3.3v j 07/25/13 update qfn package drawing. remove note on heat sink connection for qfn package. holt integrated circuits 18
0 7 detail a see detail a sq. 44pmqs 44-pin plastic quad flat pack (pqfp) .009 (.23) .520 .010 (13.20 .25) .394 .004 (10.0 .10) sq. max. .014 .003 (.37 .08) .035 .006 (.88 .15) .005 (.13) r min. .012 (.30) r max. .079 .008 (2.0 .20) .096 (2.45) max. .0315 (.80) inches (millimeters) bsc bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) hi-3585, hi-3586 package dimensions 44-pin plastic chip-scale package (qfn) package type: 44pcs bsc = ?basic spacing between centers? is theoretical true position dimension and has no tolerance. (jedec standard 95) .216 .002 (5.50 .05) .016 .002 (0.40 .05) .010 (0.25) .020 (0.50) .008 (0.2) .039 (1.00) .276 (7.00) bsc .216 .002 (5.50 .05) typ typ bottom view top view bsc .276 (7.00) bsc max inches (millimeters) electrically isolated heat sink pad on bottom of package connect to any ground or power plane for optimum thermal dissipation holt integrated circuits 19

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